Clock division in an integrated circuit is an important function for enabling the operation of the integrated circuit. In addition to dividing a clock signal, it may be necessary in many instances to provide a phase offset to the clock signal. However, providing the correct phase for the divided clock signal can increase the circuit elements required for clock division, and can also introduce potential sources of error in the clock signal. For example, a conventional circuit for providing a divided clock signal having a phase offset includes a latch after a clock divider to implement a 90 degree phase shift. However, such an implementation has many disadvantages, including the asymmetric drive strengths of the two clock paths, a requirement for additional gates that lead to jitter in the signal path, increased power consumption in the signal path, and limited phase selection of either 0+/−90 degrees. Another conventional way to achieve a configurable phase relationship is to have multiplexers at the end of each divide-by-2 block to “flip” the clock polarity if desired. However, such an arrangement also leads to jitter in the signal, and increases power requirements because of the insertion of transmission gates in the signal path.
Accordingly, improved circuits and methods for providing offset in a divided clock signal would be advantageous.